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ADT7473
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 2
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
1
ACK. BY ACK. BY
ADT7473/ADT7473 ? 1 ADT7473/ADT7473 ? 1
ADDRESS POINTER REGISTER BYTE
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
ACK. BY STOP BY
ADT7473/ADT7473 ? 1 MASTER
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 2 ADT7473/ADT7473 ? 1
FRAME 1
START BY
MASTER
ACK. BY ACK. BY
ADT7473/ADT7473 ? 1
SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER BYTE
Figure 18. Writing to the Address Pointer Register Only
STOP BY
MASTER
1
9
1
9
SCL
R/W
FRAME 1
SDA
START BY
MASTER
0
1 0 1 1 1 0 D7 D6
ACK. BY
ADT7473/ADT7473 ? 1
SERIAL BUS ADDRESS BYTE
D5 D4 D3 D2 D1
FRAME 2
DATA BYTE FROM ADT7473
D0
NO ACK. BY STOP BY
MASTER MASTER
Figure 19. Reading Data from a Previously Selected Register
Write Operations
The SMBus specification defines several protocols for
various read and write operations. The ADT7473/
ADT7473 ? 1 uses the following SMBus write protocols. The
following abbreviations are used in the diagrams:
S ? Start
P ? Stop
R ? Read
W ? Write
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
For the ADT7473/ADT7473 ? 1, the send byte protocol is
used to write a register address to RAM for a subsequent
single-byte read from the same address. This operation is
illustrated in Figure 20.
A ? Acknowledge
A ? No Acknowledge
1
S
2
SLAVE
ADDRESS
3
W A
4
REGISTER
ADDRESS
5 6
A P
Send Byte
In this operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (active low).
3. The addressed slave device asserts ACK on SDA.
Figure 20. Setting a Register Address for
Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single-byte read without asserting an intermediate stop
condition.
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